differential clock buffer/d river ddr333/pc2700-compliant cy2sstv857-27 ............. ............. document #: 38-0 7464 rev. *f page 1 of 8 400 west cesar chavez, austin, tx 78701 1+( 512) 416-8500 1+(512) 416-9669 www.silabs.com features ? operating frequency: 60 mhz to 200 mhz ? supports 266, 333 mhz ddr sdram ? 10 differential outputs from 1 differential input ? spread-spectrum-compatible ? low jitter (cycle-to-cycle): < 75 ? very low skew: < 100 ps ? power management control input ? high-impedance outputs when input clock < 10 mhz ? 2.5v operation ? pin-compatible wit h cdc857-2 and -3 ? 48-pin tssop package ? industrial temp. of ? 40 to +85c ? conforms to jedec ddr specification description the cy2sstv857-27 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. the cy2sstv857-27 generates ten differential pair clock outputs from one differ- ential pair clock input. in addition, the cy2sstv857-27 features differential feedback clock outputs and inputs. this allows the cy2sstv857-27 to be used as a zero-delay buffer. when used as a zero-delay buffer in nested clock trees, the cy2sstv857-27 locks onto the i nput reference and translates with near-zero delay to low-skew outputs. block diagram pin configuration 3 2 5 6 10 9 20 19 22 23 46 47 44 43 39 40 29 30 27 26 32 33 y0 y0# y1 y1# y2 y2# y3 y3# y4 y4# y5 y5# y6 y6# y7 y7# y8 y8# y9 y9# fbout fbout# test and powerdown logic pll 13 14 36 35 fbin fbin# clk clk# avdd 37 16 pd# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss y0# y0 vddq y1 y1# vss vss y2# y2 vddq vddq clk clk# vddq avdd avss vss y3# y3 vddq y4 y4# vss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vss y5# y5 vddq y6 y6# vss vss y7# y7 vddq pd# fbin fbin# vddq fbout# fbout vss y8# y8 vddq y9 y9# vss cy2sstv857-27
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 2 of 8 zero-delay buffer when used as a zero-delay buffer the cy2sstv857-27 will likely be in a nested clock tree application. for these applica- tions the cy2sstv857-27 offers a differential clock input pair as a pll reference. the cy2sstv857-27 then can lock onto the reference and translate with near-zero delay to low-skew outputs. for normal operation, the external feedback input, fbin, is connected to the feedback output, fbout. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll works to align the output edge with the input reference edge thus producing a near-zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when vdda is strapped low, the pll is turned off and bypassed for test purposes. power management output enable/disable control of the cy2sstv857-27 allows the user to implement power management schemes into the design. outputs are three-stated/disabled when pd# is asserted low (see table 1 ). note: 1. a bypass capacitor (0.1 ? f) should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pi ns, their high-frequency filtering characteristic will be ca ncelled by the lead indu ctance of the traces. pin description pin number pin name i/o [1] pin description electrical characteristics 13, 14 clk, clk# i differential clock input . lv differential input 35 fbin# i feedback clock input . connect to fbout# for accessing the pll. differential input 36 fbin i feedback clock input . connect to fbout for accessing the pll. 3, 5, 10, 20, 22 y(0:4) o clock outputs differential outputs 2, 6, 9, 19, 23 y#(0:4) o clock outputs 27, 29, 39, 44, 46 y(9:5) o clock outputs differential outputs 26, 30, 40, 43, 47 y#(9:5) o clock outputs 32 fbout o feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. differential outputs 33 fbout# o feedback clock output . connect to fbin# for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. 37 pd# i power down# input . when pd# is set high, all q and q# outputs are enabled and switch at the same frequency as clk. when set low, all q and q# outputs are disabled hi-z and the pll is powered down. 4, 11,12,15, 21, 28, 34, 38, 45 vddq 2.5v power supply for output clock buffers .2.5v nominal 16 avdd 2.5v power supply for pll . when vdda is at gnd, pll is bypassed and clk is buffered directly to the device outputs. during disable (pd# = 0), the pll is powered down. 2.5v nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 vss common ground 0.0v ground 17 avss analog ground 0.0v analog ground
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 3 of 8 table 1. function table inputs outputs pll avdd pd# clk clk# y y# fbout fbout# gnd h l h l h l h bypassed/off gnd h h l h l h l bypassed/off xl l hz z zz off xl h lz z zz off 2.5v h l h l h l h on 2.5v h h l h l h l on 2.5v h < 10 mhz < 10 mhz hi-z hi-z hi-z hi-z off clkin t (phase error) fbin fbout t sk(o) yx yx yx t sk(o) figure 1. phase error and skew waveforms clkin t pd yx or fbin figure 2. propagation delay time t plh , t phl
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 4 of 8 t c(n+1) yx t c(n) figure 3. cycle -to-cycle jitter pll fbin fbin# 120 ohm 120 ohm clk clk# ddr - sdram 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr _sdram represents a capacitive load ddr - sdram fbout# fbout output load capacitance for 2 ddr-sdram loads: 5 pf< cl< 8 pf figure 4. clock structure # 1 clk clk# ddr-sdram pll fbin fbin# 120 ohm 120 ohm ddr-sdram stack ddr-sdram stack 120 ohm vtr vcp 0.3" = 2.5" = 0.6" (split to terminator) ddr-sdram represents a capacitive load fbout# fbout ddr-sdram ddr-sdram ddr-sdram output load capacitancce for 4 ddr-sdram loads: 10 pf < cl < 16 pf figure 5. clock structure # 1
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 5 of 8 60 ohm receiver vcp vtr r t = 120 ohm out out# vddq 60 ohm 14 pf 14 pf vddq/2 vddq/2 vddq figure 6. differential signal using direct termination resistor
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 6 of 8 absolute maximum conditions [2] input voltage relative to v ss :............................... v ss ? 0.3v input voltage relative to v ddq or av dd : ........... v ddq + 0.3v storage temperature: ................................ ?65c to + 150c operating temperature:.................................... 0c to +85c maximum power supply: ................................................ 3.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v ddq . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v ddq ). dc electrical specifications (av dd = v ddq = 2.5v 5%, t a = 0c to +85c) [3] parameter description condition min. typ. max. unit v ddq supply voltage operating 2.38 2.5 2.63 v v il input low voltage pd# 0.3 v ddq v v ih input high voltage 0.7 v ddq v v id differential input voltage [4] clk, fbin 0.36 v ddq + 0.3 v v ix differential input crossing voltage [5] clk, fbin (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i in input current [clk, fbin, pd#] v in = 0v or v in = v ddq ?10 10 a i ol output low current v ddq = 2.375v, v out = 1.2v 26 35 ma i oh output high current v ddq = 2.375v, v out = 1v ?28 ?32 ma v ol output low voltage v ddq = 2.375v, i ol = 12 ma 0.6 v v oh output high voltage v ddq = 2.375v, i oh = ?12 ma 1.7 v v out output voltage swing [6] 1.1 v ddq ? 0.4 v v oc output crossing voltage [7] (v ddq /2) ? 0.2 v ddq /2 (v ddq /2) + 0.2 v i oz high-impedance output current v o = gnd or v o = v ddq ?10 10 a i ddq dynamic supply current [8] all v ddq , f o = 170 mhz 235 300 ma i dd pll supply current v dda only 9 12 ma i dds standby supply current pd# = 0 and clk/clk# < 10 mhz 100 a cin input pin capacitance 4pf ac electrical specifications (av dd = v ddq = 2.5v5%, t a = 0c to +85c) [9, 10] parameter description condition min. typ. max. unit f clk operating clock frequency av dd , v ddq = 2.5v ? 0.2v 60 200 mhz t dc input clock duty cycle 40 60 % t lock maximum pll lock time 100 ? s d tyc duty cycle [11] 60 mhz to 100 mhz 49.5 50 50.5 % 101 mhz to 170 mhz 49 51 % tsl(o) output clocks slew rate 20%?80% of vod 1 2 v/ns notes: 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required. 3. unused inputs must be held high or low to prevent them from floating. 4. differential input signal voltage specifies the differential voltage vtr?vcpi required for switching, where vtr is the true i nput level and vcp is the complementary input level. see figure 6 . 5. differential cross-point input voltage is expected to track v ddq and is the voltage at which the differential signal must be crossing. 6. for load conditions see figure 6 . 7. the value of voc is expected to be (vtr + vcp)/2 . in case of each clock directly terminated by a 120 ? resistor. see figure 6 . 8. all outputs switching load with 14 pf in 60 ? environment. see figure 6 . 9. parameters are guaranteed by design and char acterization. not 100% tested in production. 10. pll is capable of meeting the specified parameters while supporting ssc synthesizers with modulation frequency between 30khz and 50 khz with a down spread or ?0.5%. 11. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle = t whc /t c , where the cycle time(tc) decre ases as the fr equency goes up.
cy2sstv857 ............... ........... document #: 38-07464 rev. *f page 7 of 8 t pzl , t pzh output enable time [12] (all outputs) 325ns t plz , t phz output disable time [12] (all outputs) 38ns t ccj cycle to cycle jitter [10] f > 66 mhz ?75 ? 75 ps tjit(h-per) half-period jitter [10, 13] f > 66 mhz ?100 ? 100 ps t plh( t pd) low-to-high propagation delay, clk to y test mode only 1.5 3.5 7.5 ns t phl( t pd) high-to-low propagation delay, clk to y 1.5 3.5 7.5 ns t sk(o) any output to any output skew [14] 100 ps t phase phase error [14] ?50 50 ps notes: 12. refers to transition of non-inverting output. 13. period jitter and half-period jitter specif ications are separate specifications that must be met independent ly of each other . 14. all differential input and output terminals are terminated with 120 ? /16 pf, as shown in figure 5 . ac electrical specifications (av dd = v ddq = 2.5v5%, t a = 0c to +85c)(continued) [9, 10] parameter description condition min. typ. max. unit
cy2sstv85 ............... ........... document #: 38-07464 rev. *f page 8 of 8 the information in this document is believed to be accurate in all respects at the time of p ublication but is subject to change without notice. sil- icon laboratories assumes no responsibility for errors and omissi ons, and disclaims responsibil ity for any consequences resulti ng from the use of information included herein. additi onally, silicon laboratories assumes no res ponsibility for the functioning of undescr ibed features or parameters. silicon laboratories reserves the right to make c hanges without further notice. silicon laboratories makes no warra nty, repre- sentation or guarantee regarding the suitability of its produc ts for any particular purpose, nor does silicon laboratories assu me any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon labor atories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other a pplication in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratorie s products for any such unintended or unauthor ized appli- cation, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. package drawing and dimension ordering information part number package type product flow cy2sstv857zc-27 48-pin tssop commercial, 0 ? to 70 ? c CY2SSTV857ZC-27T 48-pin tssop?tape and reel commercial, 0 ? to 70 ? c cy2sstv857zi-27 48-pin tssop i ndustrial, ?40 to +85c cy2sstv857zi-27t 48-pin tssop?tape and reel industrial, ?40 to +85c 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48
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